1. Field of the Invention
The present invention relates to the programing of cells in a memory array. More particularly, the present invention relates to a method for programing memory cells in a flash memory array while avoiding bit line leakage current which may be created by overerased cells in the array.
2. Description of the Related Art
FIG. 1 shows a cross section of a typical flash EEPROM array cell 2. The cell 2 is formed on a substrate 4 having a source 6 and drain 8 provided adjacent to its surface. Separated from the substrate 4 by an oxide layer is a floating gate 10 which is further separated from a control gate 12 by an additional oxide layer.
In one method for programing termed hot electron injection, a current is established between the source 6 and drain 8 while a large positive voltage is typically established between the control gate 12 and drain 8. For instance, during programing a typical gate voltage V.sub.g may be set to 13 V while a drain voltage V.sub.D is set to 6 V and the source voltage V.sub.s is grounded. The large positive gate-to-drain voltage enables electrons flowing from the source to drain to overcome an energy barrier existing between the substrate 2 and the oxide underlying the floating gate 10 enabling the electrons to be driven onto the floating gate 10. The electrons stored on the floating gate 10 increase the cell threshold voltage (the gate-to-source voltage required for a cell to turn on or conduct).
To represent a data bit, the floating gate 10 is programmed to store a charge as described above. In a programmed state, the threshold voltage of cells is typically set at greater than 6.5 volts, while the threshold voltage of cells in the erased state is typically limited below 3.0 volts. To read a cell, a control gate voltage between the 3.0 and 6.5 volt range, typically 5 V, is applied. With 5 V applied to the gate, in a programmed state with a threshold above 6.5 V, a current will not conduct between the drain and source, but in an erased state with a threshold below 3.0 V a current will conduct.
To erase the cell 2, a positive source to drain voltage is applied along with a large positive source to gate voltage. For instance, during erase a typical gate voltage V.sub.G may be set to -10 V while the source voltage V.sub.s is set to +5 V and the drain is floated. The large positive source-to-gate voltage enables electrons to tunnel from the floating gate 10 reducing the threshold voltage of the cell.
FIG. 2 illustrates how memory cells of FIG. 1 are configured in an array. FIG. 2 includes a 3.times.3 array of memory cells 200, similar to those in FIG. 1, although a larger number of cells may be utilized. Drains of a column of memory cells in the memory cells 200 are connected to one of bit lines BL0-BL2. Gates of a row of memory cells in memory cells 200 are connected to one of word lines WL0-WL2. Sources of all memory cells in the array 200 are typically connected to ground.
Power is supplied to the individual word lines and bit lines by a power supply 202 to control programming, erase and read operations. Power is supplied to word lines WL0-WL2 through a wordline decoder 204. The wordline decoder provides a signal from the power supply 202 to the word lines WL0-WL2 as controlled by a wordline address signal received by the wordline decoder.
In a flash memory array, all cells are typically erased simultaneously. Erasing of the memory cells is typically done by repeated applications of a short, approximately 10 msec, erase voltage, described above, applied to each of the cells over the word lines.
After each application of the erase voltage, a read or verify wordline voltage of typically 5.0 V is applied from the power supply 202 to a row of memory cells over a wordline. Additionally, the 5.0 V read or verify wordline voltage is supplied from the power supply 202 to reference cells 208. An example of circuitry for reference cells 208 is included in U.S. Pat. application Ser. No. 08/160,582 entitled "Programmed Reference." Voltage is further applied from power supply 202 to bit lines of memory cells 200 and bit lines of reference cells 208 to create current from bit lines BL0-BL2 of memory cells 200 which is then received in sense amplifiers 206 along with current from at least one output from reference cells 208. Typically during verify, the current output of a reference cell having a 3.0 V threshold is compared with current from each of bit lines BL0-BL2 in sense amplifiers 206. If bit line current generated from a particular cell in memory cells 200 is less than that of the reference cell with the 3.0 V threshold, indicating the particular cell threshold is above the 30 V limit, additional erase pulses are applied until the current of the particular cell is equal to or greater than current from the reference cell with the 3.0 V threshold.
One problem caused by overerased cells is bit line leakage current during programming. To program a selected cell, a positive voltage is applied to the bit line connected to the selected cell while a positive word line voltage is applied to a row of cells containing the selected cell with source lines grounded. The voltages applied to the selected cell create the positive drain to source voltage and the large positive gate to drain voltage, as described previously, to enable hot-electron injection in the selected cell. During programming wordlines of unselected cells are grounded. With an overerased cell on the bit line of the selected cell, zero volts on the gate of the overerased cell will be above its threshold causing it to conduct a bit line leakage current. A bit line leakage current during programming may overload the power supply current available.
Bit line leakage current is a significant concern when a charge pump is required in the power supply 202 to pump the bit line voltage above V.sub.cc during programming. A charge pump may be required for low power devices, such as 3 V devices currently utilized with battery powered notebook computers, to pump the voltage above 3 V during programming. Requiring the charge pump size to be further increased during programming to overcome any bit line leakage current is undesirable.
To prevent current leakage during programming, manufacturers may utilize a convergence method to place a minimum threshold limit on all cells. Several different convergence methods are employed by manufacturers.
In one convergence method, a voltage, such as 6 V, is applied to the source of erased memory cells while the gates and drains of the erased cells are grounded to create a drain disturb voltage. The effect of the drain disturb voltage causes the threshold voltages erased below 0 V to converge to a steady-state threshold voltage of approximately 0 V. See, for example, "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM," by S. Yamada et al. (Yamada), IEEE Tech. Dig. IEDM 1991, pp. 307-310.
In another convergence method, a voltage, such as 6 V is applied to the source of erased memory cells while grounding the drains, but applying a gate voltage above 0 V. The effects of the increased gate voltage enables voltages which would converge to approximately 0 V in Yamada to converge to a steady-state threshold voltage above 0 V. See, for example, U.S. Pat. application Ser. No. 08/160,057 entitled "An Adjustable Threshold Convergence Circuit", by J. Chen, et al. (Chen), filed Dec. 1, 1993.
A problem with the convergence methods of Yamada and Chen is that significant power is required for convergence. Significant power use results from the number of overerased cells which have a threshold voltage less than zero volts. When the drain disturb voltage is applied utilizing a gate to source voltage of zero volts, the overerased cells will conduct. With cells conducting, additional current is necessary to maintain the drain disturb voltage. By increasing the gate voltage above zero volts as disclosed in Chen, even more cells will conduct, thus further increasing the current required for convergence.
To reduce leakage current during convergence, another method for converging the threshold voltage distribution of memory cells after erase is described in U.S. Pat. application Ser. No. 08/269,540 entitled "Multistepped Threshold Convergence for a Flash Memory Array", by N. Radjy et al. (Radjy), filed Jul. 1, 1994, and incorporated herein by reference. In Radjy, a drain disturb voltage is applied to one or more bit lines of a memory array, similar to Yamada and Chen. However, instead of applying a single gate to source voltage of 0 V as in Yamada or a more positive value as in Chen, Radjy starts the overerase correction with a negative gate to source voltage and then increases the gate to source voltage until a desired minimum threshold value is reached. By applying a gate voltage with an initial negative value, overerased cells which have a higher threshold than the gate voltage will not conduct, reducing leakage current during convergence in comparison to both Yamada and Chen.
Although Yamada, Chen and Radjy enable convergence of the threshold values of erased cells, a possibility still may exist that cells have a negative threshold. Overerased cells may still remain particularly when the convergence method of Yamada is utilized because by converging thresholds to approximately 0 V, a significant number of cells with a slightly negative threshold can remain.